The present invention relates to a semiconductor memory and concerns a nonvolatile ferroelectric memory for storing data by using characteristics of a ferroelectric capacitor.
In recent years, of nonvolatile memories, a nonvolatile ferroelectric memory has become a focus of attention. The nonvolatile ferroelectric memory stores data by using characteristics of a ferroelectric capacitor, dramatically improves the number of times of rewriting as compared with a flash memory and an EEPROM, and increases a reading speed and a writing speed with a low source voltage.
First, the following will briefly describe operations of the ferroelectric memory having the above characteristics.
FIG. 10 is a circuit block diagram showing a configuration of a conventional ferroelectric memory. As shown in FIG. 10, the ferroelectric memory is constituted by a memory M10 including a memory cell MC10 and a precharge circuit PC10, and a memory control section MS10 for controlling the memory cell MC10 and the precharge circuit PC10. The memory cell MC10 has a 2T (transistor)/2C (capacitor) configuration. FIG. 11 is a timing chart showing control signals in the memory control section MS10 of the ferroelectric memory shown in FIG. 10.
In FIGS. 10 and 11, reference character XEXTCE denotes an external input control signal, reference character INTCE denotes an internal circuit control signal, reference character WL denotes a word line, reference characters BL and /BL denote bit lines, reference character CP denotes a cell plate electrode, reference character BP denotes a bit line precharge control signal, reference character SAE denotes a sense amplifier control signal, reference character VSS denotes a ground voltage, reference character SA denotes a sense amplifier, reference numerals CM0 and CM0B denote memory cell capacitors using a ferroelectric material, reference numerals QnWL1, QnWL2, and QnBP0 to QnBP2 denote N-channel MOS transistors, reference numeral 100 denotes a CE initial-stage circuit for producing the internal circuit control signal INTCE from the external input control signal XEXTCE, and reference numeral 101 denotes a control circuit for producing signals WL, CP, BP, and SAE from the internal circuit control signal INTCE.
The bit lines BL and /BL are connected to the sense amplifier SA, and the sense amplifier SA is controlled by the sense amplifier control signal SAE.
The first electrode of the memory cell capacitor CM0 is connected to the bit line BL via the memory cell transistor QnWL1 whose gate electrode is connected to the word line WL.
The second electrode of the memory cell capacitor CM0 is connected the cell plate electrode CP. The first electrode of the memory cell capacitor CM0B, which is paired with the memory cell capacitor CM0, is connected to the bit line /BL via the memory cell transistor QnWL2 whose gate electrode is connected to the word line WL. The second electrode of the memory cell CM0B is connected to the cell plate electrode CP.
Further, the bit lines BL and /BL are connected to each other via the N-channel MOS transistor QnBP0. The bit line BL and the ground voltage VSS, and the bit line /BL and the ground voltage VSS are respectively connected to the N-channel MOS transistors QnBP1 and QnBP2. The gate electrodes of the N-channel MOS transistors QnBP0 to QnBP2 are controlled by the bit line precharge control signal BP.
The memory cell capacitors CM0 and CM0B store a logical state (xe2x80x9c1xe2x80x9d or xe2x80x9c0xe2x80x9d) of data depending upon an electrical polarization state of ferroelectric capacitors constituting the memory cell capacitors CM0 and CM0B. When a voltage is applied between the electrodes of the memory cell capacitors CM0 and CM0B, the ferroelectric material is polarized in a direction of an electric field.
Referring to FIG. 11, the following will briefly discuss the reading operation of the ferrorelectric memory configured thus.
FIG. 11 is a timing chart showing the control signals for exercising memory control in the conventional ferroelectric memory. As shown in FIG. 11, in an initial state, the external input control signal XEXTCE activated at logical voltage xe2x80x9cLxe2x80x9d is at logical voltage xe2x80x9cHxe2x80x9d, the internal circuit control signal INTCE is at logical voltage xe2x80x9cLxe2x80x9d, the bit line precharge control signal BP is at logical voltage xe2x80x9cHxe2x80x9d, and the bit lines BL and /BL are at logical voltage xe2x80x9cLxe2x80x9d. Moreover, the word line WL, the cell plate electrode CP, and the sense amplifier control signal SAE are at the ground voltage VSS, which is at logical voltage xe2x80x9cLxe2x80x9d.
Firstly (at timing of time T1), since the external input control signal XEXTCE is set at logical voltage xe2x80x9cLxe2x80x9d, the internal circuit control signal INTCE is changed to logical voltage xe2x80x9cHxe2x80x9d and the bit line precharge control signal BP is changed to logical voltage xe2x80x9cLxe2x80x9d. Hence, the bit lines BL and /BL are brought into a floating state.
Next, at timing of time T2, the word line WL and the cell plate electrode CP are set at logical voltage xe2x80x9cHxe2x80x9d, and data of the memory cell capacitors CM0 and CM0B is read to the bit lines BL and /BL.
And then, at timing of time T3, the sense amplifier control signal SAE is set at logical voltage xe2x80x9cHxe2x80x9d, data is amplified, the reading operation is started, and data of the memory cell capacitors CM0 and CM0B is rewritten in two states of logical voltage xe2x80x9cHxe2x80x9d of the cell plate electrode CP after the amplification of data and logical voltage xe2x80x9cLxe2x80x9d of the cell plate electrode CP.
Next, at timing of time T4, since the sense amplifier control signal SAE is set at logical voltage xe2x80x9cLxe2x80x9d, the operation of the sense amplifier SA is suspended. And then, at timing of time T5, since the bit line precharge control signal BP is set at logical voltage xe2x80x9cHxe2x80x9d, the bit lines BL and /BL return to a logical voltage xe2x80x9cLxe2x80x9d and a potential across the memory cell is made equal.
Subsequently, at timing of time T6, the word line WL is set at logical voltage xe2x80x9cLxe2x80x9d, the bit lines BL and /BL and the memory cell are made unconnected with each other and are brought into the initial state.
As described above, in addition to during the writing operation, the ferroelectric memory performs rewriting during and after the reading operation. Further, as compared with a flash memory demanding a high voltage for rewriting data, just because of a difference in potential across the memory cell capacitor, charge is transferred and the rewriting operation is carried out. Thus, it is quite important to protect data from a malfunction even at a low voltage.
Considering the operations when the power is turned on and off on a ferrorelectric memory section (memory section M10 of FIG. 10) and a logical section (memory control section MS10 of FIG. 10) including a microcomputer for controlling the memory section, control signals produced from the microcomputer (logic) section may be undefined. In this case as well, data needs to be protected.
Moreover, considering the timing of suspending the operation, the operation of the microcomputer (logic) section can be immediately suspended without any problems. However, regarding the ferroelectric memory requiring rewriting after reading, data needs protection during the operation.
Therefore, even at a voltage other than a guaranteed source voltage, particularly at a low voltage when the power is turned on and off, it is not possible to maintain nonvolatile characteristics unless data is protected by exercising control for avoiding a reading operation and a writing operation based on the relationship between a source voltage and a potential of an external control signal.
Hence, regarding the ferroelectric memory, the presence of a circuit, which detects a source voltage value, prevents a malfunction in response to a detection signal, and protects stored data, is more important than a conventional nonvolatile memory. A source voltage detection circuit configured as below is required as a circuit capable of operating thus.
Referring to FIG. 12, the following will discuss a source voltage detection circuit in the conventional ferroelectric memory.
FIG. 12 is a circuit diagram showing the configuration of the source voltage detection circuit in the conventional ferroelectric memory. In FIG. 12, reference numerals QpA11 to QpA16 denote P-channel MOS transistors, reference numerals QnA11 and QnA12 denote N-channel MOS transistors, reference numerals 111 and 112 denote inverter circuits, reference character VDD denotes a source voltage, and reference character VSS denotes a ground voltage.
The source of the P-channel MOS transistor QpA11 is connected to the source voltage VDD, and the gate and drain thereof are connected to a node N111. The source of the P-channel MOS transistor QpA12 is connected to the source voltage VDD, the gate thereof is connected to the node N111, and the drain thereof is connected to a node N113.
The P-channel MOS transistors QpA14 and QpA15 are connected in series between the node N111 and the node N112, and the N-channel MOS transistor QnA11 connects the node N112 and the ground voltage VSS. The P-channel MOS transistors QpA14 and QpA15, which are connected in series, and the N-channel MOS transistor QnA11 act as resistors.
The inverter circuit 111 connects the node N113 and the ground voltage VSS. The inverter circuit 111 has the node N112 as an input terminal and the node N115 as an output terminal. The inverter circuit 111 has the P-channel MOS transistor QpA13 and the N-channel MOS transistor QnA12 connected in series.
The input terminal of the inverter circuit 112 is connected to the node N115, and a signal VOUT10 is obtained at the output terminal of the inverter circuit 112. The P-channel MOS transistor QpA16 connects the node N115 and the source voltage VDD. The signal VOUT10 is supplied to the gate of the P-channel MOS transistor QpA16.
In the source voltage detection circuit configured thus, the output node VOUT10 judges if a potential is higher or lower than a detected potential. When a potential is below a detected potential, e.g., when the source is turned on or off, an operation such as resetting an internal circuit is carried out.
Regarding the source voltage detection circuit in such a conventional ferroelectric memory, in the case where the P-channel MOS transistors QpA11, QpA14, and QpA15 have a threshold value (Vt) of Vtp1 and the N-channel MOS transistor QnA11 has a threshold value (Vt) of Vtn1, a detected potential is about 3* Vtp1+Vtn1.
Assuming a threshold value (Vt) of the transistor is 0.4 V due to a variation range including variations in process and temperature, it is expected that a detection level is largely varied by (3*0.4+0.4=1.6 V).
Particularly, considering a 3 V-ferroelectric memory in which a source voltage VDD is lowered, a difference is narrowed between a detection level and a lower limit voltage for guaranteeing the operation. Due to variations in process, if a voltage of the detection level is higher, the detection level is set at or higher than a lower voltage limit of the guarantee. When a product specification is not satisfied or when a voltage of the detection level is lower, the detection level is set at a low voltage preventing a normal operation. In the worst case, it is expected that no detection signal is produced. Thus, it is not possible to positively protect data as expected due to fluctuations in threshold value (Vt) of the transistor. The threshold value is changed due to fluctuations in process and temperature.
Besides, regarding the ferroelectric memory, standardization is not made on an entry method (e.g., WCBR method of DRAM) of a special test mode, which is different from a normal operation. However, like an endurance (the number of rewriting times) test, a reliability estimation test requires an extremely long time in a normal operation. Thus, it is necessary to shorten time by entering a test mode being different from the normal one. Further, it is also necessary to avoid device breakage when a high voltage stress is applied.
The present invention is devised to solve the above conventional problems. The object of the present invention is to provide a ferroelectric memory, in which data can be positively protected using a voltage detection signal stabilized at a constant potential by reducing variations in voltage detection level, the variations being resulted from fluctuations in process parameter, and since a reliability estimation test is carried out in a test mode being different from a normal operation, it is possible to shorten time and to prevent device breakage caused by high-voltage stress for evaluating reliability.
The ferroelectric memory of the present invention, in which data is stored by allowing an internal control signal produced based on an external input control signal to conform electrical polarization of a ferroelectric capacitor to a logical state of data, and the stored data is read by the internal control signal, is provided with a memory control section including a divided potential generating circuit for generating a divided potential, which is divided based on a source voltage with a constant ratio; a reference potential generating circuit for generating a constant reference potential, which is independent of the source voltage, according to a predetermined detection level relative to the source voltage; a differential amplifier circuit for outputting logical voltage according to a potential difference between the reference potential and the divided potential; and control signal producing means for producing the internal control signal based on the external input control signal or a logical voltage from the differential amplifier circuit, wherein the memory control section is configured such that when the source voltage is detected as being lower than the detection level based on a logical voltage from the differential amplifier circuit, while the external input control signal is deactivated, the stored data is protected by the internal control signal produced based on a logical voltage from the differential amplifier circuit.
Further, the ferroelectric memory of the present invention, in which data is stored by allowing an internal control signal produced based on an external input control signal to conform electrical polarization of a ferroelectric capacitor to a logical state of data, and the stored data is read by the internal control signal, is provided with a memory control section including a divided potential generating circuit for generating a divided potential, which is divided based on a source voltage with a constant ratio; a reference potential generating circuit for generating a constant reference potential, which is independent of the source voltage, according to a predetermined detection level relative to the source voltage; a differential amplifier circuit for outputting a logical voltage according to a potential difference between the reference potential and the divided potential; power supply detection means for outputting a detection signal of the power supply only for a fixed time after the power is turned on for supplying the source voltage; and control signal producing means for producing the internal control signal based on the external input control signal, the power supply detection signal, or a logical voltage from the differential amplifier circuit, wherein the memory control section is configured such that when the source voltage is detected as being lower than the detection level by a logical voltage from the differential amplifier circuit or when the power supply is detected by the power supply detection signal, while the external input control signal is deactivated, the stored data is protected by the internal control signal produced based on the power supply detection signal or a logical voltage from the differential amplifier circuit.
Moreover, the ferroelectric memory of the present invention is configured such that as a predetermined detection level relative to the source voltage, a detection level is set higher when the power is turned on as compared with when the power is turned off.
Besides, the ferroelectric memory of the present invention is configured such that capacitor elements are connected as additional circuits to the output nodes of the reference potential generating circuit and the divided potential generating circuit.
According to the above configurations, it is possible to protect data with stability by using the source voltage detection circuit for reducing variations in voltage detection level to stabilize the detection level, the variations being resulted from fluctuations in process parameter.
The ferroelectric memory of the present invention, in which data is stored by allowing an internal control signal to conform electrical polarization of a ferroelectric capacitor to a logical state of data, and the stored data is read by the internal control signal, is provided with a memory control section including a divided potential generating circuit for generating a divided potential, which is divided based on a source voltage with a constant ratio; a reference potential generating circuit for generating a constant reference potential, which is independent of the source voltage, according to a predetermined detection level relative to the source voltage; a differential amplifier circuit for outputting logical voltage according to a potential difference between the reference potential and the divided potential; and a test mode entry circuit for outputting a test mode signal as the internal control signal based on a logical voltage from the differential amplifier circuit, the test mode signal allowing the entry of a test mode being different from a normal operation, wherein the memory control section is configured such that when the source voltage is detected as being higher than the detection level based on a logical voltage from the differential amplifier circuit, the entry of the test mode is allowed according to a logical voltage from the differential amplifier circuit.
According to the above configuration, the entry of the test mode is possible without providing a special input terminal.
The ferroelectric memory of the present invention, in which data is stored by allowing an internal control to conform electrical polarization of a ferroelectric capacitor to a logical state of data, and the stored data is read by the internal control signal, is provided with a memory control section including a divided potential generating circuit for generating a divided potential, which is divided based on a source voltage with a constant ratio; a reference potential generating circuit for generating a constant reference potential, which is independent of the source voltage, according to a predetermined detection level relative to the source voltage; a differential amplifier circuit for outputting logical voltage according to a potential difference between the reference potential and the divided potential; and a booster circuit for outputting a boosted voltage signal, which is controlled in a direction of boosting a potential, as the internal control signal based on a logical voltage from the differential amplifier circuit, wherein the memory control section is configured such that when the source voltage is detected as being higher than the detection level based on a logical voltage from the differential amplifier circuit, an output potential of the booster circuit is controlled according to a logical voltage from the differential amplifier circuit.
According to the above configuration, it is possible to prevent excessive stress without providing a special input terminal.
Moreover, the ferroelectric memory of the present invention is configured such that as a predetermined detection level relative to the source voltage, a detection level is set higher when the power is turned on as compared with when the power is turned off.
Besides, the ferroelectric memory of the present invention is configured such that capacitor elements are connected as additional circuits to the output nodes of the reference potential generating circuit and the divided potential generating circuit.
According to the above configurations, the entry of the test mode is possible without providing a special input terminal, and excessive stress can be prevented without providing a special input terminal.
As described above, it is possible to protect data with stability by using a source voltage detection circuit for stabilizing a detection level by reducing variations in voltage detection level that are resulted from fluctuations in process parameter.
Therefore, it is possible to use a voltage detection signal stabilized at a constant potential and to positively protect data.
Further, the entry of a test mode is possible without providing a special input terminal.
Hence, it is possible to shorten time by conducting a reliability estimation test in a test mode being different from a normal operation.
Moreover, it is possible to prevent excessive stress without providing any special input terminal.
Thus, it is possible to avoid device breakage caused by applying a high-voltage stress for estimating reliability.